Conventional optical projection lithography has been the standard silicon patterning technology for the past 20 years. It is an economical process due to its inherently high throughput, thereby providing a desirable low cost per part or die produced. A considerable infrastructure (including steppers, photomasks, resists, metrology, etc) has been built up around this technology.
In this process, a mask, or “reticle”, includes a semiconductor circuit layout pattern typically formed of opaque chrome, on a transparent glass (typically SiO2) substrate. A stepper includes a light source and optics/lenses that project light coming through the reticle and images the circuit pattern, typically with a 4× to 5× reduction factor, on a photo-resist film formed on a silicon wafer. The term “chrome” refers to an opaque masking material that is typically but not always comprised of chrome. The transmission of the opaque material may also vary such as in the case of an attenuating phase shift mask.
As the semiconductor industry continues to evolve, feature sizes of the pattern are driven to smaller resolution. To meet this demand, Resolution-Enhanced optical lithography Technologies (“RET”) have become popular as techniques for providing patterns with sub-wavelength resolution. These methods include off-axis illumination (“OAI”), optical proximity correction (“OPC”), and phase-shift masks (“PSMs”). Such resolution-enhanced optical lithography methods are especially useful for generating physical devices on a wafer that require small size and tight design tolerance. Examples of such physical devices are the gate length of a transistor or the dimensions of contact cuts formed in inter-layer dielectrics.
One of the most common commercial implementations of phase shift mask technology is the double exposure method. A first mask, often called a binary mask, contains most of the features at the gate level. The binary mask can be printed using standard lithography techniques. A second mask, often called an alternating phase-shift mask (altPSM) includes the critical, or small sized features at the gate level.
An example of a double exposure phase shift method is illustrated in FIGS. 1A and 1B. FIG. 1A shows a layout of the mask features including the binary gate mask and phase shift features needed for each phase shift printed transistor. FIG. 1A shows a layout 100 of the overlay of a binary photomask and an altPSM over active areas 102. The binary photomask includes a series of binary gate layouts 112. The altPSM includes the phase shifters (also called shifters) 122a and 122b, where phase shifters 122a have a 0° phase shift and phase shifters 122b have a 180° phase shift. In use, a photoresist is applied to a wafer and the wafer is exposed to both masks in succession followed by photoresist development. The final transistors 132 and 134 formed using the two masks shown in FIG. 1A are shown in FIG. 1B.
At least one phase shifter is placed on a side of a feature that is to be reduced in size. In FIG. 1A, shifters 122a and 122b are placed on both sides of gate layouts 112. The features that are to be reduced in size are often placed next to other features, which themselves are to be reduced in size. As such, there is a limited amount of space in which to place the shifters. In FIG. 1A, for example, shifter 122b is placed in the space D1. In this case, the shifter 122b has a width D2 sufficiently less than the size of the space D1 and can be placed into the allotted space.
Problems arise, however, when designing an altPSM used to produce regions of a layouts having dense features and isolated features, such as arrays of transistors in random logic designs and where features are perpendicular to each other. For example, the width of phase shifters for isolated lines must be optimized to give maximum process margin. The optimal solution often produces shifter widths that are large in comparison to the spaces in the layout in which they must fit. Conventional layouts, however, use the same size default shifter for each feature to be reduced in size. The conventional methods are incapable of varying the shifter size so the shifter cannot be optimized to fit in the allotted space. As a result, problems arise, some of which are illustrated in FIGS. 2A-2C.
For example, in FIG. 2A gate layout 212a is spaced at the same distance from gate layout 212b as gate layout 212c is spaced from gate layout 212d and gate layout 212b is spaced a distance D2 from gate layout 212C, where D1 is different than D2. A space having width D3 is allotted for shifters on the sides of gate layout 212a and gate layout 212b that face each other and the space D3 is also allotted for shifters on the sides of gate layout 212c and gate layout 212d that face each other. The space having width D4 is allotted for shifters in the space having distance D2 on the sides of gate layout 212b and gate layout 212c that face each other. The space D1 is different from the space D2 because gate layout 212b is separated from gate layout 212c by a different amount than gate layout 212a is separated from gate layout 212b. As mentioned, conventional methods are only capable of using the same shifter width, shown here as width D5, for all situations. Thus, shifters 222a and 222b that have the same width D5 are used in each space D4 and D3, respectively. Because gate layouts 212a and 212b and gate layouts 212c and 212d are spaced close together, the shifters having width D5 fill almost all of the allowable space D3, which causes the gate features to print incorrectly. Similarly, gate layout 212b is spaced far from gate layout 212c. The shifters having width D5 do not provide an appropriate amount of coverage, which also causes the gate features to print incorrectly.
As shown in FIG. 2B, trying to fit the shifters of width D6 into a space of width D7 causes the shifters to merge into a single shifter. While in some cases merged shifters may be acceptable, in many cases, merged shifters cannot be used as they incorrectly trim the printed features or fail to reproduce an intended feature on a substrate. FIG. 2C depicts another example of a case where merged shifters are unacceptable. In FIG. 2C, gate layout 212 is perpendicular to gate layout 216 and the shifters 222a, 222b, 226a, and 226b, which are the same standard size, overlap. In this case, the merged shifters cause the gate features to print incorrectly.
Accordingly, the present invention solves these and other problems of the prior art to provide a method that can design layouts having maximum and/or variable shifter widths to allow altPSM implementation for dense or existing layouts.